Active-matrix liquid crystal display devices are capable of providing a color or black and white gradation display in accordance with an inputted video signal, and therefore have been used until now for notebook computers and computer monitors. However, in recent years, as they offer an increased number of tones and enhanced resolution, they have been also used for electronic appliances, such as cell phones, car navigation systems, and television receivers.
FIG. 9 is a block diagram illustrating the overall configuration of a conventional active-matrix liquid crystal display device used in such an electronic appliance. As shown in FIG. 9, the liquid crystal display device includes a liquid crystal panel (display portion) 100 having a number of pixel formation portions arranged in a matrix, a display control circuit 200, a gate driver (scanning signal line drive circuit) 300, a source driver (video signal line drive circuit) 400, a reference voltage generation circuit 500, a common electrode drive circuit 600, and a power supply voltage generation circuit 700.
The liquid crystal panel 100 has a liquid crystal layer sandwiched between two opposing insulation substrates. On one substrate, gate bus lines (scanning signal lines) GL and source bus lines (video signal lines) SL are arranged in a matrix, and pixel formation portions are provided in the vicinity of their intersections. The pixel formation portions each include a pixel electrode Ep and a common electrode Ec, in which the pixel electrode is connected to the source bus line SL via a TFT (Thin Film Transistor) 10, and the common electrode is disposed on the other substrate.
Liquid crystals, when having direct-current voltage continuously applied thereto, solidify in a certain direction and become immobile, leading to the “burn-in” phenomenon. Accordingly, in order for liquid crystals not to experience the “burn-in” phenomenon, it is necessary to perform alternating-current drive in which the pixel electrode Ep repeatedly alternates in predetermined cycles between potentials higher and lower than a voltage VCOM at the common electrode Ec.
The display control circuit 200 generates various timing control signals and a digital video signal DV in order to operate the gate driver 300, the source driver 400, and the common electrode drive circuit 600, based on image data DAT and a timing control signal TS, which are transmitted externally.
When the display control circuit 200 outputs timing control signals GCK and GSP to the gate driver 300, the gate driver 300 sequentially selects each gate bus line GL for one horizontal period based on the received timing control signals GCK and GSP, and outputs an active scanning signal to the selected gate bus line GL. Also, the display control circuit 200 outputs to the source driver 400 the externally transmitted image data DAT as a digital video signal DV representing video to be displayed, along with timing control signals SCK, SSP, and LS.
The source driver 400 converts the digital video signal DV received from the display control circuit 200 into a drive video signal, which is an analog video signal, via a selector (also referred to as a “D/A converter”). Concretely, the selector selects a drive video signal in order to perform alternating-current drive on the liquid crystal layer, from among two types of analog voltages (hereinafter, referred to as “gradation voltages”) generated for gradation display based on two types of gradation reference voltages VH1 to VH3 and VL1 to VL3 inputted from the reference voltage generation circuit 500, the gradation voltages being alternatingly selected in accordance with the digital video signal DV. The source driver 400 applies the drive video signal obtained by the conversion to the pixel electrode Ep via the source bus line SL at times determined by the timing control signals SCK, SSP, and LS.
On the other hand, the common electrode drive circuit 600 applies the common voltage VCOM to the common electrode Ec. As a result, a pixel capacitance consisting of the pixel electrode Ep and the common electrode Ec is charged with the common voltage VCOM and the voltage supplied by the drive video signal applied to the pixel electrode Ep, so that desired video is displayed on the liquid crystal panel 100.
The power supply voltage generation circuit 700, when having a reference voltage of 12 volts externally applied thereto, generates and outputs a power supply voltage for each circuit via an internal DC/DC converter. Note that FIG. 9 shows only an analog power supply voltage VLS and a base gradation voltage VKB, which are included in the generated power supply voltages, with the remaining other power supply voltages being omitted.
The reference voltage generation circuit 500 includes a voltage dividing circuit 51 and operational amplifiers OP1 to OP6, in which the voltage dividing circuit extracts necessary voltages from nodes for six resistances R1 to R6 connected in a series, and the operational amplifiers are connected to their corresponding nodes in the voltage dividing circuit 51. The voltage dividing circuit 51 has applied to one terminal a base gradation voltage VKB of 15.2V from the power supply voltage generation circuit 700 with the other being grounded. The resistances R1 to R6 have their resistance values determined in accordance with gamma characteristics (the relationship between voltage applied to the liquid crystal panel and brightness) of the liquid crystal panel 100 to be used. To perform alternating-current drive on the liquid crystal layer, there are three gradation reference voltages, which are first to third gradation reference voltages VH1 to VH3 (hereinafter, referred to as “VH-side gradation reference voltages”), required for generating gradation voltages higher than the common electrode VCOM (hereinafter, referred to as “VH-side gradation voltages”), and another three gradation reference voltages, which are first to third gradation reference voltages VL1 to VL3 (hereinafter, referred to as “VL-side gradation reference voltages”), required for generating gradation voltages lower than the common electrode VCOM (hereinafter, referred to as “VL-side gradation voltages”).
The first to third VH-side gradation reference voltages VH1 to VH3 and the first to third VL-side gradation reference voltages VL1 to VL3 generated by the voltage dividing circuit 51 are voltages extracted from the nodes for the resistances R1 to R6 in the voltage dividing circuit 51 and outputted to the source driver 400 via the operational amplifiers OP1 to OP6. The operational amplifiers OP1 to OP6 output the voltages inputted from the nodes for the resistances R1 to R6 after conversion into low-impedance output voltages.
To perform alternating-current drive on the liquid crystal layer, the source driver 400 requires the following equation (1), which is called the “driver's rule”, to be satisfied among an analog power supply voltage VLS of 15.6V, a withstand reference voltage VBD half the analog power supply voltage, the VH-side gradation reference voltages VH1 to VH3, and the VL-side gradation reference voltages VL1 to VL3.VLS>VH1 to VH3>VBD>VL1 to VL3>GND  (1)In the source driver 400, when equation (1) is not satisfied, excess current flows between the terminal for the analog power supply voltage VLS and the ground terminal, so that the selector does not operate normally, resulting in no video being displayed on the liquid crystal panel 100.
Accordingly, a study is made as to whether or not equation (1) is satisfied for the VH- and VL-side gradation reference voltages VH1 to VH3 and VL1 to VL3 generated by the reference voltage generation circuit 500.
FIG. 10 is a graph illustrating over-time changes of the gradation reference voltages in the conventional art. In FIG. 10, the gradation reference voltages VH1 to VH3 and VL1 to VL3, which rise from the ground voltage GND to their respective predetermined voltage values, are represented by solid lines, and the analog power supply voltage VLS and the withstand reference voltage VBD are represented by one-dot chain lines. It is appreciated from FIG. 10 that the VH-side gradation reference voltages VH1 to VH3 always fall between the analog power supply voltage VLS and the withstand reference voltage VBD, and the VL-side gradation reference voltages VL1 to VL3 fall between the withstand reference voltage VBD and the ground voltage GND. Accordingly, it is appreciated that the gradation reference voltages VH1 to VH3 and VL1 to VL3 generated by the reference voltage generation circuit 500 always satisfy equation (1).
Therefore, even when the gradation reference voltages VH1 to VH3 and VL1 to VL3 generated by the reference voltage generation circuit 500 are applied to the source driver 400, no excess current flows between the terminal for the analog power supply voltage VLS in the source driver 400 and the ground terminal. Note that the mechanism of excess current flowing when equation (1) is not satisfied will be described later.
Japanese Laid-Open Patent Publication No. 2003-84725 discloses a reference voltage generation circuit in which a voltage dividing circuit having a plurality of resistances connected in a series performs resistive division on power supply voltage to generate gradation reference voltages. Also, Japanese Laid-Open Patent Publication No. 2005-43435 discloses a liquid crystal driver in which a sequencer is provided between an instruction driver and a power supply, and controls the timing of writing a set value to the instruction driver.
[Patent document 1] Japanese Laid-Open Patent Publication No. 2003-84725
[Patent document 2] Japanese Laid-Open Patent Publication No. 2005-43435